downloaded by vinve fu of olivetti on friday, 20 september, 2002 12:15:09 am PM8355 4-channel 2.125, 2.5, and 3.125 gbit/s transceiver with half-rate support quadphy-ii? pmc-2000791 (p6) proprietary and confidential to pmc - sierra, inc., and for its customers? internal use ? copyright pmc - sierra, inc. 2002 general description the quadphy-ii? is a physical layer transceiver ideal for systems requiring high-speed point-to-point communi- cation links. it is applicable for pma- pmd connections in 10 ge, infiniband 1 or 4 x 2.5 gbit/s links, 1 and 2 gbit/s fibre channel, as well as high speed serial backplanes for high capacity systems. features general 10gbit/s, bi-directional, xaui to xgmii link compatible with ieee 802.3ae. four independent 2.125, 2.5 and 3.125 gbit/s serdes for fibre channel, infiniband, 10 ge line cards and high-speed backplane applications. half/full rate mode selectable per channel. integrated serializer/ deserializer, clock synthesis, clock recovery and 8b/10b encode/decode logic. low-power operation 1.5 w typical @ 3.125gbit/s. serial i/o redundant high-speed serial i/o channels for convenient switching to redundant fabric. high-speed outputs with optional pre- emphasis to drive longer backplanes. high-speed i/o with on-chip termination resistors to directly drive dual-terminated 50 ohm lines. high-speed inputs have programmable receive equalization to eliminate the effects of inter symbol interference (isi). parallel i/o 10-bit dual data rate (ddr) parallel interface. selectable source simultaneous or source synchronous transmit and receive parallel interfaces. convenient output clock for user friendly asic timing. interoperates with sstl2 and 1.8 v lvcmos standard. trunking &timing integrated receive fifo synchronizes incoming data to local clock domain. trunking feature de-skews and aligns all four channels to form a single 10 gbit/s logical link. test features extensive control of loopback, bist, and operating modes via 802.3 compliant mdc/mdio serial interface. on-chip packet generator/checker- provides at-speed diagnostics. built-in error counters per channel. support for ieee 1149.1 jtag testing on all pins. physical 1.8v,0.18 standard cmos technology with 2.5 v tolerant i/o. 289-ball cabga (19 mm x 19 mm package). applications high speed serial backplanes 10gelinks fibre channel transceivers infiniband transceivers xaui retimers intra-system interconnect refclk serializer 8b/10b encoder fifo & /a/ insert adaptive sampler clock recovery de- serializer &byte align 10b/8b decoder fifo & trunking logic serial loopback parallel loopback channel a channel b channel c channel d txda [9:0] txclk rxclka common control logic 9or10 9or10 reset, mdio/mdc mode strapping pins jtag interface, bist pins clock synthesis pll_lock sysclk tdoxpa/ tdoxna tdoypa/ tdoyna 2 2 rdixpa/ rdixna rdiypa/ rdiyna 2 2 PM8355 - quadphy-ii rxda [9:0] primary channel primary channel secondary channel secondary channel xaui transmit xaui receive xgmii parallel output xgmii parallel input block diagram
downloaded by vinve fu of olivetti on friday, 20 september, 2002 12:15:09 am head office: pmc-sierra, inc. 8555 baxter place burnaby, b.c. v5a 4v7 canada tel: 604.415.6000 fax: 604.415.6200 4-channel 2.125, 2.5, and 3.125 gbit/s transceiver with half-rate support to order documentation, send email to: document@pmc-sierra.com or contact the head office, attn: document coordinator pmc-2000791 (p6) ? copyright pmc-sierra, inc. 2002. all rights reserved. octalphy, quadphy, and s/uni are registered trademarks of pmc-sierra inc. spectra, chess and quadphy-ii are trademarks of pmc-sierra, inc. proprietary and confidential to pmc-sierra, inc., and for its customers? internal use PM8355 quadphy-ii? all product documentation is available on our web site at: http://www.pmc-sierra.com for corporate information, send email to: info@pmc-sierra.com example architecture the figure below shows a multi-service switching platform using quadphy-ii devices for backplane interconnect and client signal physical interfaces. as a serial backplane transceiver, the redundant high-speed links simplify the interface to a working and protect fabric. the 10ge line cards use the quadphy- ii as a phy supporting xaui on the line side and mating to a 10ge mac using xgmii. infiniband and fibre channel line cards applications are also shown. the half- rate mode of the quadphy-ii enables 1 and 2 gbit/s support using the same device. the other applications shown are a xaui retimer and an xgmii extender where the mac and optics module separated by longer distance. optical tranceiver 1gig fibre channel link 1gig fibre channel link tbi optical tranceiver 2gig fibre channel link 2gig fibre channel link tbi quadphy-ii serial 10 gigabit ethernet lan line card custom asic upper layer functions mac 10 ge 10gig serial lan xgmii xaui xenpak or xpak wdm 10 gigabit ethernet lan line card custom asic upper layer functions mac 10 ge 4x3.125 wdm xgmii xaui optical xceivers gigabit ethernet gigabit ethernet gmii/tbi switch fabric device redundant switch fabric device switch fabric module 10 gigabit ethernet lan line card xgmii asic or fpga xaui extender xaui retimer 10 ge lan xaui quad/ octal phys quad/ octal phys quadphy-ii quadphy-ii quadphy-ii quadphy-ii quadphy-ii quadphy-ii quadphy-ii quadphy-ii quadphy ii quadphy-ii quadphy-ii quadphy-ii quadphy-ii quadphy-ii quadphy-ii quadphy-ii nxge macs upper layer functions asic / fpga fiberchannel mac + upper layer functions asic / fpga fiberchannel mac + upper layer functions quadphy-ii quadphy-ii quadphy-ii infiniband line card 4x2.5 gig fibre infiniband asic upper layer functions mac xgmii 4x2.5gig quadphy-ii quadphy-ii 1g fibre channel card 1g / 2g fibre channel card gigabit ethernet card xenpak or xpak xenpak or xpak xenpak or xpak application example - multi-service switching platform
|
